1. Technical Field
The present invention relates to data processing systems in general and, in particular, to data processing systems having a hierarchial cache memory architecture. Still more particularly, the present invention relates to a method and apparatus for forwarding data in a hierarchial cache memory architecture.
2. Description of the Prior Art
A data processing system typically includes a processor coupled to a variety of storage devices arranged in a hierarchial manner. Hardware and/or software can dynamically allocate parts of the storage devices within the hierarchy for addresses deemed most likely to be accessed soon. The type of storage employed in each hierarchical level relative to the processor is normally determined by balancing the requirements for speed, capacity, and cost.
In addition to a main memory, a commonly employed storage device in the hierarchy includes a high-speed memory known as a cache memory. A cache memory speeds the apparent access times of the relatively slower main memory by retaining the instructions and/or data that the processor will most likely access again soon, and making the instructions and/or data available to the processor at a much lower latency. As such, cache memory enables relatively fast access to a subset of instructions and/or data that were recently transferred from the main memory to the processor, and thus improves the overall speed of the data processing system.
A multi-level cache memory hierarchy is a cache memory system consisting of several levels of cache memories, each level having a different size and speed. Typically, the first level cache memory, commonly known as the level one (L1) cache, has the fastest access time and the highest cost per bit as compared with the other levels of cache memories. The remaining levels of cache memories, such as level two (L2) caches, level three (L3) caches, etc., have a relatively slower access time but also a relatively lower cost per bit. Typically, each higher cache memory level has a progressively slower access time and a lower per-bit cost. The present disclosure provides a method and apparatus for forwarding data within a hierarchial cache memory architecture.
In accordance with a preferred embodiment of the present invention, a cache memory hierarchy includes multiple levels of cache memories, each level having a different size and speed. A command is initially issued from a processor to the cache memory hierarchy. If the command is a Demand Load command, data corresponding to the Demand Load command is immediately forwarded from a cache having the data to the processor. Otherwise, if the command is a Prefetch Load command, data corresponding to the Prefetch Load command is held in a cache reload buffer within a cache memory preceding the processor.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.